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最新猎头职位
作者: 时间:2017-2-14 阅读:

 

系统设计总监  工作地点 : 广东 珠海市 
岗位职责:
    1、制定系统研发的方向和目标,制定短中期的产品研发思路及可行性方案;
    2、参与重大系统开发项目的管理;
    3、负责系统研发中心的团队建设和日常运营。
岗位要求
任职条件:
1、电子类或者相关专业本科以上学历;
2、5年以上系统设计开发经验 ;
3、具有良好的系统设计项目管理和开发团队管理经验,至少3年的实际项目开发管理和10人以上团队管理经验;
4、具备全面的技术研发能力,拥有过硬的技术功底和良好的系统工程思想;
5、有良好的沟通能力与分析能力;
6、具备良好的心理素质和工作承压能力,工作认真、踏实,责任心强。
 
 
FPGA工程师 工作地点 : 广东 广州市
职位描述
1.参与研发项目的立项、系统构架及方案制定;
2.分解系统需求,进行相关FPGA代码编写、调试以及维护;
3.负责无线通讯相关的标准技术预研;
4.研究无线通信协议,并完成相关算法设计;
5.负责基带传输系统的仿真、验证及系统联调工作;
岗位要求
1.电子/通信等相关专业, 本科以上学历;
2.丰富的CPLD/FPGA项目开发经验,本科5年以上、研究生3年以上的工作经历;
3.熟练使用各种综合、仿真、验证及调试工具;
4.熟悉C或Matlab,熟练使用HDL和FPGA完成通信算法的硬件实现工作;
5.熟悉产品开发流程,良好的编码风格和文档编写能力;
6.有无线通讯系统、基带信号处理及相关产品开发经验者优先,有带领团队进行项目开发工作经验者优先;
7.高度的责任心和团队协作能力,能承受较大的工作压力;
 
 
Sr. DSP Engineer 工作地点 : 上海
职位描述
Implement and optimize video and image processing algorithm based on OpenGL, OpenCL, or based on CPU and CPU’s coprocessor on android os or iOS.
Requirement:
Familiar with OpenGL, OpenCL 
Familiar Game Engine
Familiar with Graphics and Display related technology of android OS or iOS.
岗位要求
Requirement:
Familiar with OpenGL, OpenCL 
Familiar Game Engine
Familiar with Graphics and Display related technology of android OS or iOS.
 
 
Sr. IC Engineer  工作地点 : 上海
职位描述
1. SOC architecture definition and coordination including clock/reset structure definition, low power partition definition, etc.
2. Full chip timing closure, work closely with backend for tape out sign off
3. Define UPF/CPF, verify low power structure base on RTL or NETLIST level
4. Understand DFT/synthesis flow, provide necessary support
5. Video or processor related IP level micro-architecture definition, RTL design, co-work with verification owner
岗位要求
Requirements
1. BS or above in microelectronics, electrical engineering or equivalence
2. 3~5 year experience of ASIC EDA tool and front-end design/coding. Video chip experience is preferred.
3. Must have one of following EDA tool experience
a) STA, low power, DFT, synthesis
4. Must have one of following design/coding experience, video related is preferred
a) IP level micro-architecture definition, RTL design, co-work with verification owner
5. Nice to have experience of chip level clock/reset structure definition, low power partition definition
6. Good team work and communication skill (both in Chinese and English).
 
高级模拟电路工程师  工作地点 : 上海 
职位描述
1. 设计有挑战性的模拟电路,比如ADC, DAC, LDO,PLL,BANDGAP,MIXER等;
2. 指导后端工程师实现模拟电路的Layout设计;
3.按照模块的规格和芯片总体方案承担模块的详细设计和实施工作并确保研发的按时按质完成。
岗位要求
1. 微电子等相关专业,硕士及以上学历,扎实的模拟电路理论知识,具备实际模拟电路产品设计经验者优先; 
2.8年以上模拟集成电路或Analog/Mixed-signal电路全流程设计经验; 
3.精通PLL和低功耗等电路; 
4.有ADC/DAC等相关成功流片经验优先; 
5. 熟悉各种模拟集成电路模块设计和分析,如:ADC/DAC/LDO/PLL/Vco/Bgap/Charge Pump/Opamp等; 
6. 能使用相关EDA工具如Cadence、Hspice等仿真工具对不同电路性能进行仿真; 
7.有很强的独立工作能力,协助研发团队进行开发工作; 
8.熟悉基本数字电路设计,熟悉I2C; 
9.良好的英文阅读写作能力,团队合作能力和协调沟通能力;
10.如有海外经验优先。
 
 
DFT工程师  工作地点 : 北京
职位描述
 
1. DFT technology/methodology research and development;
2. Project execution: develop test plan for mix-signal and digital design including SerDes testing;
3. Project execution: test design simulation, test vector generation and verification on ATE;
 
任职要求
1.More than 2 years working experience.
2.Knowledge or courses (taken) of Logic design, Microelectronics Circuit, Basic Electromagnetism are required; Knowledge and experience on Fault/Test Synthesis, ATPG and BIST algorithms;
3.Master or PHD
4.E.E or Microelectronics or Computer Science
5.Good Mandarin and English
6.Integrity, Cooperative, Active
 
 
Sr./Staff verification Engineer 工作地点 : 上海
职位描述
Responsibilities:
Responsibilities will include developing verification environment; developing test plans for and verifying the function of ASIC; hands-on implementation work for every aspect of ASIC verification, working closely with the system group, architects, design and verification teams. The successful candidate should have experience going through at least one complete and successful ASIC design/verification cycle from architecting and creating ASIC test environment to full completion of the verification work. The candidate also needs to have a full understanding of design using Verilog and working experience with SystemVerilog. A strong communication skill in both Chinese and English is required.
岗位要求
Qualifications:
 
5+ years of ASIC verification experience, complex SOC verification experience is preferred
 
Strong programming skills in SystemVerilog
 
Knowledgeable in Verilog/Verilog-PLI/SystemC/SVA/C/C++
 
Working Experience with UVM/OVM/VMM (at least one of them)
 
Responsible for implementation of verification environment and generation of high quality test cases.
 
BS/MS EE, CE or CS
 
 
数字IC设计高级工程师   工作地点 : 上海
职位描述
1、负责数字IC电路设计,参与制定芯片规格,编写相关设计文档 
2、RTL coding,仿真验证,综合与时序分析 
3、FPGA验证芯片功能 
4、和测试人员共同制定量产测试方案,并协助调试
岗位要求
1、电子类相关专业,本科或本科以上学历 
2、3-5年数字IC设计经验
3、熟悉数字IC设计流程,熟练掌握verilogHDL coding,DC/PT/FT等工具 
3、有FPGA设计经验者优先 
4、工作认真负责、善于学习、具有良好的团队合作精神
 

 

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