Senior ASIC designer for CPU/Security
We are looking for ASIC engineer to define/design/verify/deploy our digital IP for in-house embedded CPU and security engine, which are widely used in many GPU and Tegra chips. The candidate will act as the key member of ASIC team.
The candidate's responsibilities include:
1. Define architecture/micro architecture for our digital IP in CPU and security domain.
2. IP ASIC design & signoff, including RTL coding, fix timing, performance and power optimization, etc;
3. Verification to ensure IP quality;
4. IP integration to SOC
1. BS or above degree in CS/EE with solid knowledge base in ASIC design
2. 2+/3+ years of experiences in front-end digital IP design and experience in CPU and security would be a good plus.
3. Strong Verilog programming ability, familiar with all kinds of frond-end ASIC design flow & design tools;
4. Strong programming skills in C/C++, PERL/Makefile preferred, familiar with Linux Env
5. Strong communication skills, good English in both oral and literal, can drive cross-site/cross-countrycollaborations efficiently.